This invention relates to drive circuitry for plasma display panels. In particular, this invention consists of circuitry particularly suited for implementing non-coincident techniques for writing and erasing in a panel. Non-coincident drive systems use methods of applying drive pulses on the respective orthogonal drive lines in a display in which the drive pulses for a particular display element are not pulsed at the same time for any particular operation. This invention shows novel drive circuitry using charge storage diodes for implementing the particular drive methods shown. The circuitry is also used to implement the dual-on-state (DOS) method of operation in the display panel.
Of particular pertinence in the prior art in U.S. Pat. No. 3,906,451 issued to the present inventor and assigned to the same assignee. This patent relates to a method and apparatus for non-coincident erase selection in a plasma display panel.
Another patent of particular pertinence in the prior art is U.S. Pat. No. 3,786,474 which relates to a non-coincident method for writing in a plasma display panel.
Two other patents which are of particular pertinence to this application are U.S. Pat. Nos. 3,689,912 and 3,851,212 both of which relate to plasma panel drive circuits and in which charge storage diodes are used to implement some of the features of the disclosure.
Another patent in the prior art is U.S. Pat. No. 3,969,718, issued to the present inventor and assigned to the same assignee, which discloses the operation and function of the dual-on-state in a plasma display panel.
While the above referenced patents will give the reader an insight to the plasma display panel art and work which is related to the present invention, it will be helpful here to discuss in greater detail the theory on which the present invention is developed. Large area plasma display panels, built on the high frequency inherent capacity, memory system of operation, presents challenging problems in the area of design of high performance selection circuitry. Display panels having 1024 by 1024 electrodes and active display areas on the order of about one meter square present large capacitive loads to the drive circuitry. One important design consideration is that drive circuitry for plasma display panels have a low internal impedance so that short rise time pulses may be applied to the panel electrodes. Short rise time pulses are desirable because the best margin in write and erase selection operations may be obtained using such pulses. One common selection method uses a resistor-diode matrix to select display electrodes using a reduced number of driver switching elements. This resistive decoupling method gives speed and power problems when the electrode capacitance exceeds 100 pf. Another selection method uses individual low impedance drivers on each display electrode. This method solves the circuit problem but presents some serious economic problems in producing large display panels.
The use of charge storage diodes (hereinafter CSD) in a selection matrix provides some important advantages in a plasma display selection method. Using CSD elements provides selectable low impedance switches for each of the display electrodes. A CSD is a high voltage diode which has a relatively long reverse recovery time. A low voltage driver/clamp selection matrix selectively forward biases a CSD prior to the application of the desired write or erase pulse. Because of the long reverse recovery time, the selected CSD provides a low impedance path to drive the display electrode. Unselected CSD elements block the selection pulse by the normal high reverse impedance of the diode.
A timing method for applying selection pulses to a plasma display seems to be well adapted to the CSD circuit implementation. This approach called non-coincident selection, is a method in which a full amplitude write or erase pulse is applied on one axis, only, of the orthogonal display electrodes. The pulse is made selective or non-selective by appropriate preconditioning or postconditioning of the display elements. In contrast, the more common selection method presently used requires that coincident positive and negative half-select pulses be applied to opposing display electrodes in the orthogonal array.
It is desired in a large scale plasma display panel to have several characteristics which may be provided by use of the invention described in this application. It is desirable to have as high speed as possible for each of the write and erase functions as well as other operations so that the plasma display panel can have the display changed or updated as rapidly as possible. Of course, with larger and larger numbers of individual display elements shorter functional time per display element becomes more important for each particular operation. It is desirable to have low voltage drive circuitry because low voltage drive and selection elements are considerably less expensive than comparable elements which will operate at high voltage. For example low voltage transistors, operating at approximately 15 volts, may be used in circuitry employing CSDs. These transistors are considerably less expensive than any appropriate high voltage transistors. Another factor is that the entire drive circuitry be built from as few possible number of individual circuit types as possible. The present invention shows a system which has a minimum number of individual circuit types from which the entire system is developed. Also, in large panels it is more and more difficult to achieve reliable writing of display elements and the present invention allows implementation of the dual-on-state method of writing in a display panel. And finally, the present invention has the advantage of providing low impedance drive characteristics for the drive circuitry to allow fast rise time pulses.